In this article, we propose a technique to accelerate nonvolatile or hybridof volatile and nonvolatile processor cache design space exploration forapplication specific embedded systems. Utilizing a novel cache behaviormodeling equation and a new accurate cache miss prediction mechanism, ourproposed technique can accelerate NVM or hybrid FIFO processor cache designspace exploration for SPEC CPU 2000 applications up to 249 times compared tothe conventional approach.
展开▼
机译：在本文中，我们提出了一种针对特定嵌入式系统加速非易失性或易失性和非易失性处理器缓存设计空间探索的技术。与传统方法相比，我们提出的技术利用新颖的缓存行为建模方程式和新的精确的缓存未命中预测机制，可以将SPEC CPU 2000应用程序的NVM或混合FIFO处理器缓存设计空间探索速度提高了249倍。
展开▼
